瑞典专利SE1350595A1 Bipolar transistor amplifier circuit with isolated gate

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24 Abstract The present invention provides a lateral IGBT transistor comprising' a bipolar transistor~ and. an IGFET. The lateralIGBT comprises a low resistive connection between the drainof the IGFET and the base of the bipolar transistor, and an isolating layer arranged between the IGFET and the bipolar transistor. The novel structure provides a device which isimmune to latch and. gives high. gain and reliability. Thestructure can be realized with standard CMOS technology available at foundries. H:DOCWORK130515 Application textdocx, 2013-05-15 130017SE
公开号:SE1350595A1
申请号:SE1350595
申请日:2013-05-16
公开日:2014-11-17
发明作者:Klas-Håkan Eklund
申请人:Klas Håkan Eklund Med K Eklund Innovation F；
IPC主号:

专利说明:

An Insulated Gate Bipolar Transistor Amplifier circuit Technical Field The present invention relates to an insulated gate bipolar transistor (IGBT) device. In particular, the present inven- tion relates to a hybrid form of semiconductor devices com- bining a field effect transistor with a bipolar transistor.
Background of the inventionOver the recent years a growing interest has been seen in thearea of highly integrated semiconductor device that can be used for power management and signal amplification.
U.S. patent No. 5,126,806 describes a lateral insulated gate bipolar transistor (IGBT), Ref.l, which is particularly well suited for high power switching applications. Disclosed is an enhancement-IGFET device having its source and drain elec- trodes connected to the base and emitter, respectively, of a lateral bipolar transistor. When an appropriate gate input voltage, here in the form of a positive charge, is applied to the IGFET, the channel conducts, thus biasing' the bipolar transistor into conduction. The applied charge on the gate electrode can be used to control a large current through the bipolar device, which is of particular interest in power applications. Safe switching operation at high voltages how-ever requires a very wide base and a low gain in the bipolartransistor. Various forms of said devices have been integrat-ed in modern CMOS processes as described by Bakeroot et.al.416-418, 2007, Ref.2. in IEEE EDL-28, pp. Relevant in this context is also a report by' E. Kho Ching' Tee entitled. “A review of techniques used in Lateral Insulated Gate Bipolar(LIGBT)” in Journal of Electrical and Electronics pp.35-52, 2012, Transistor Engineering, vol.3, Ref.3. While this type of device is potentially quite useful for various forms of power H:DOCWORK130515 Application textdocx, 2013-05-15 130017SE switching, with its requirements of high voltage capability and. low internal gain, it is disadvantageous for* a device incorporated in a low voltage highly integrated circuit in- tended for power management and signal amplification.
FIG. lA shows one example of prior art in the form of a lat-eral insulated gate bipolar transistor device (LIGBT) such asdescribed. in U.S. Patent No. 5,l26,806 by Sakurai et.al. mentioned above. The integrated device 30 is constructed in alow-doped n-type layer 35 containing a p-type doped layer 50with a higher impurity concentration than that of the n-typelayer and a p+ layer 70 with an impurity concentration ex-ceeding that of the p-type doped layer 50. In the p-dopedlayer 50 is provided an n+-layer 60 with an impurity concen-tration that is higher than that of the p-type layer 50. Thep-doped layer 50 and the n+-layer 60 are electrically short-circuited by an emitter electrode 55. A collector electrode65 forms an ohmic contact to the p+-layer 70. An insulating film. serves as gate dielectric 40 and separates the gate electrode 45 from the substrate.
When a positive potential is applied to the gate electrode45, the conductivity of a surface portion of the p-layer 50under the gate dielectric 40 is inverted to form an n-typechannel. Electrons from the n+-layer 60 can then pass throughthe channel fronl the n- layer' 35 to the _p+-layer* 70 from which positive holes are injected. Thereby the n- layer 35, having a high resistivity, is conductivity-modulated to pro-vide a low resistance path between the anode (C) and cathode(E) in FIG. lA. A low on-resistance and. excellent forwardblocking characteristic can thus be realized, which is quite useful for various forms of power switching.
H:DOCWORK130515 Application textdocx, 2013-05-15 130017SE Numerous modifications of the above described embodiment, with emphasis on improved switching performance, exist, some of which are covered in a report entitled “A review of tech- niques used in Lateral Insulated Gate Bipolar Transistor (LIGBT)” by E. Kho Ching Tee published in Journal of Electri- cal and Electronics Engineering, vol.3, pp.35-52, 20l2.
FIG. IB, is an equivalent electrical circuit diagram for the device in FIG. IA. Shown are the three terminals, C, E and G.
The device also utilizes an external back-side substrate electrode. The n-type IGFET has its source and body terminals strapped together at (E) and these are, in turn, connected to the collector layer (C) of the lateral bipolar pnp-transistor over* the body' resistance, Rl. Shown. is also how the base terminal of the lateral pnp-transistor is connected to the drain of the IGFET over a variable resistance, R2, the latter mirroring the conductivity modulation.
A vertical parasitic npn-transistor that has its base con- nected. to the collector of the lateral pnp-transistor is included in FIG. IB to illustrate that the LIGBT contains a thyristor-like structure. Once this thyristor causes latch- up, the LIGBT device can no longer be controlled by the gate potential. The condition for latch-up is: dwn + amp 2 I, where dmm and dmm are the common-base current gains of theparasitic npn transistor and pnp transistor, respectively. To reduce the risk for latch-up it is essential to lower the current gain d in both transistors. Since the pnp transistor carries the on-state voltage drop, the gain of the npn-transistor has to be suppressed by, e.g., increasing the basedoping below the emitter layer (lowering the base re- sistance).
H:DOCWORK130515 Application textdocx, 2013-05-15 130017SE Summary of the inventionObviously prior art hybrid semiconductor devices need to beimproved, particularly with regards to the latch-up, in order to be commercially attractive as amplifying circuits.
The object of the present invention is to provide an IGBTdevice that overcomes the drawback of the prior art devices.
This is achieved by the device as defined in claim l.
A lateral IGBT transistor is provided comprising a bipolartransistor and an IGFET having a low resistive connectionbetween the drain of the IGFET and the base of the bipolartransistor and an isolating layer arranged between the IGFETand the bipolar transistor, thereby providing latch immunity.According to one embodiment of the invention the lateral IGBTtransistor is a lateral n-channel IGBT transistor comprisingThe lateral a bipolar pnp transistor and a n-channel IGFET. n-channel IGBT transistor comprises a semiconductor sub- strate, and an insulating layer buried in the semiconductorsubstrate and at least covering the bipolar pnp transistor.The bipolar pnp transistor comprises: -a p-type collector layer arranged on top of a portion ofinsulating layer and extending to the upper surface of thesemiconductor substrate, forming the collector of the bipolarpnp transistor; -an n-type base layer arranged within the p-type collectorlayer and extending to the upper surface of the semiconductorsubstrate, forming the base of the bipolar pnp transistor;and, -a p-type emitter layer arranged within n-type base layer andsurface of the semiconductor sub- extending' to the upper strate, forming the emitter of the bipolar pnp transistor.
H:DOCWORK130515 Application textdocx, 2013-05-15 130017SE The n-channel IGFET comprises: -a p-well extending from the upper surface of the semiconduc-tor substrate into the semiconductor substrate; -a channel layer* in vicinity' of the upper* surface of thesemiconductor substrate and arranged under a gate structure;-an n-type source layer forming the source of the n-channelIGFET; and-an n-type drain layer forming the drain of the n-channelIGFET.
According to the embodiment the lateral n-channel IGBT tran-sistor is provided with: -an n-well layer adjacent to the p-well of the n-channelIGFET and to the collector layer of the bipolar pnp transis-tor. The n-type base layer is enclosed by the collector lay-er. The n-well layer surrounds the collector layer and is incontact with insulating layer, providing device isolation ofthe bipolar pnp transistor, -a low resistive interconnect layer extending from the drainlayer to the base layer forming low resistive interconnectand simultaneously providing an ohmic contact to the baselayer. The low resistive interconnect layer is arranged atleast partly over the p-well and at least partly over the collector layer and at least partly over the n-well layer.
According to another embodiment of the invention the lateralIGBT transistor is a lateral p-channel IGBT transistor com- prising a bipolar npn transistor and a p-channel IGFET.
The lateral p-channel IGBT transistor comprises a semiconduc-tor substrate and a buried n-layer arranged in the semicon-ductor substrate at least covering the bipolar npn transistor and at least portion of a drain layer of the IGFET.
The bipolar npn transistor comprises: H:DOCWORK130515 Application textdocx, 2013-05-15 130017SE -an n-type collector layer arranged on top of a portion ofthe buried n-layer and a portion extending to the upper sur-face of the semiconductor substrate, forming the collector ofthe bipolar npn transistor; -a p-type base layer arranged within the n-type collectorlayer and extending to the upper surface of the semiconductorsubstrate, forming the base of the bipolar npn transistor;and -an n-type emitter layer arranged within base layer and ex-semiconductor substrate, tending' to the upper forming the emitter of the bipolar npn transistor.
The p-channel IGFET comprises: -an n-well extending from the upper surface of the semicon-ductor substrate into the semiconductor substrate; -a channel layer* in vicinity' of the upper* surface of thesemiconductor substrate and arranged under a gate structure;-a p-type source layer is forming the source of the p-channelIGFET; and-a p-type drain layer forming' the drain of the p-channel IGFET.
According to the embodiment the lateral p-channel IGBT tran-sistor is provided with: -a p-well layer adjacent to the p-well of the p-channel IGFETand to the collector layer of the bipolar npn transistor. Thep-type base layer is enclosed by the collector layer and thep-well layer surrounds the collector layer and is in contactwith the buried n-layer providing device isolation betweenthe IGFET and the npn bipolar transistor;-a low resistive interconnect layer extending from the drainlayer to the base layer forming low resistive interconnectand simultaneously providing an ohmic contact to the base layer.
H:DOCWORK130515 Application textdocx, 2013-05-15 130017SE The low resistive interconnect layer* is arranged. at least partly over the n-well, at least partly over the collector layer and at least partly over the p-well layer.
According to a further embodiment the semiconductor substrateof the lateral IGBT transistor comprises a buried oxide layerand the insulating layer is formed by the oxide layer that extends over the complete substrate.
According to a further embodiment the interconnect layer of the lateral IGBT transistor' is provided. with openings to allow contact to the collector layer.
According to yet a further embodiment the interconnect layer l36c is shunted by a silicide layer of low resistivity.
According to yet a possible further embodiment the intercon-nect layer is replaced by a metal bridge spanning from drain layer of the IGFET to base layer of the bipolar transistor.
If the interconnect layer is replaced by a metal bridge layer130 in Fig.2 it may be connected to the highest potentialwhich is the potential at the emitter layer 145 instead offollowing the varying base potential with a lot of capaci-tance variations. Further layer l25a can be withdrawn from layer l20.
For the p-channel device in Fig.3 layer 220 can be withdrawnfrom layer 230a so that layer 225 will be in contact with the substrate ll5 and normally be at ground potential.
According to yet a further embodiment the lateral IGBT tran-sistor is provided with oxide isolation layers surrounding the emitter and the collector contact layers.
H:DOCWORK130515 Application textdocx, 2013-05-15 130017SE Latch-up immunity is a key performance advantage and is re-lated to the killed gain of the lateral pnp-transistor in Fig.2 where layer 145 is the emitter layer, 136c is the e.g.base layer and 125 is the collector layer. The low resistanceof the base layer will effectively kill the gain of the tran- sistor and related collector current will be zero.
This will also prevent layer 135 from being forward biasedagainst layer 125a which is the first step to latch-up. Thiswill also drastically reduce substrate current which is an-other key performance advantage.
The latch-up immunity' will allow the gain of the bipolar transistor 102 to be optimized for very high gain typically100-500.
The bipolar transistor 102 can further optionally drive thebase of an npn-transistor like 202 in a Darlington connection where the gains are multiplied to be well over 10000.
With this internal amplification the device can be used for power management and signal amplification and many other types of electronic circuits as near field. communication, opto electronics and charge detection in sensor applications.Further the n-channel device in Fig. 2 can easily be combined on the same chip with the p-channel device in Fig. 3.
To further improve voltage capability for e.g. power manage- ment the IGFET could be of the extended drain type.
In the preferred embodiment the device can be realised in a standard low-voltage CMOS process as provided by foundries.
H:DOCWORK130515 Application textdocx, 2013-05-15 130017SE And can therefore easily be combined with standard CMOS logic and analogue functions.
Brief description of the drawingsWhile the novel features of the invention are set forth withboth as particularity in the appended claims, the invention, to organization and content, will be better understood and appreciated from the following detailed description and draw- ings, in which: FIG. IA is a sectional side view depicting a representativeprior art lateral insulated gate bipolar transistor (LIGBT),and FIG IB is the equivalent circuit of the prior-art device inFIG. 1A.
FIG. 2 illustrates schematically' the structure of a first embodiment of the IGBT according to the present invention.FIG. 3 illustrates schematically the structure of a secondembodiment of the IGBT according to the present invention.
FIG. 4 illustrates schematically' the structure of a thirdembodiment of the IGBT according to the present invention.FIG. 5 illustrates schematically the structure of a fourth embodiment of the IGBT according to the present invention.
Detailed description The present invention will now be explained with the help ofthe accompanying drawings which show embodiments thereof.
In Fig. 2 is shown a preferred embodiment of a lateral N-channel IGBT transistor 100 which easily can be combined withstate of the art CMOS technology. Said IGBT consists of anIGFET transistor IOI that is electrically connected to the base of a bipolar pnp transistor IO2 as described below.
H:DOCWORK130515 Application textdocx, 2013-05-15 130017SE The substrate 115 consists of a silicon wafer with or without an epi layer on top. Said substrate 115 is preferably of (100)-orientation. Substrate 115 can also, in an embodiment of the invention, be a Silicon-On-Insulator (SOI) substrate.
In case an SOI substrate is used layer 120 is omitted.
Within a part of the substrate a buried n-type layer 120 with a typical thickness in the order of 1 um and a typical doping 4 concentration in the range of 1-10” to 1-10” cm is formed.
On top of a part of layer 120, a p-type layer 125b is formed that reach the surface. Said layer 125b has a thickness around 0.6um.znMí a doping concentration around 1-1018 cm%.The layer 125b will form the collector of the bipolar pnp transistor.
Within layer 125b an n-type layer 127b is formed that reachthe surface and forms the base of the bipolar pnp transistor.
The n-type base layer 127b has a doping concentration in the 3 range of 5-10” to 5-10w cm- and the base-collector junction is approximately 0.3 um below surface. Said n-type base layer127b is enclosed by the collector layer 125b. Within layer127b a p+-layer 145 which reach the surface is formed. The junction depth of said p+ layer is approximately 0.2 um and the layer has a typical surface doping concentration of5-1019 cm%. Said layer, which is enclosed by the base layer127b, forms the emitter of the bipolar pnp transistor.
The n-type IGFET transistor is located in the p-well 125a with its channel layer 126 in vicinity of the semiconductor surface, right under the gate structure 156. The n+-layer 135 is forming the source of the IGFET and the n+-layer 136a the drain of the IGFET. The junction depths of said n+-layers are approximately' 0.2 um. and the layers have typical surface in the range of 5-1019 to 1-1020 cm%. concentrations A p+- H:DOCWORK130515 Application textdocx, 2013-05-15 130017SE ll layer 140 with a typical junction depth of 0.2 um and a typi- 4 cal surface doping concentration of 5-10” cm will serve as substrate contact.
The n-type IGFET is separated from the Bipolar transistor byan n-type layer 130 that is placed on top of, and makes con- tact to, layer 120. Said layer reaches the surface and verti-cally surrounds the p-type layer 125b that forms the collec-tor of the pnp transistor. The thickness of said layer isapproximately 0.4 um and the doping concentration is around1-10” cmf. On top of layer 130 is a low resistive intercon-nect layer 136c arranged that extends into layers 125a and125b to interconnect layers 136a and 136b, forming respective drain and base contact layers of the devices.
The layer 130 will isolate the bipolar pnp transistor fromthe substrate together with layer 120. The highly doped drainlayer 136a forms an ohmic contact to the IGFET and the highlydoped layer136b forms an ohmic contact to the base layer 127b of the pnp-transistor, where layer 145 is the emitter and layer 125b is the collector. The n+-layer 136c contain open- ings before reaching layer 125b leaving space for contacting the collector layer with a p+-layer, 142. The surface of said interconnect layer is preferably shunted by a silicide layerTiSi2, NiSi) CoSi2, of low resistivity. As indicated in (e.g.
Fig. 2, the p-layer 125a, the contact p+-layer 140, the n+- source 135, the gate electrode 156 and drain layer 136a canbe mirrored in the vertical plane 122 through the emitter.For about the preferred embodiment of the device in Fig.2 again more than 100 has been verified with a base-width ofaround 0.4um which means there is a lot of room for improve-ments. In Fig. 3 is shown a preferred embodiment of a lateralP-channel IGBT transistor 200 which easily can be combined with state of the art CMOS technology. Said IGBT consists of H:DOCWORK130515 Application textdocx, 2013-05-15 130017SE l2 a p-type IGFET transistor 20l that is electrically connectedto the base of za bipolar npn transistor 202 as described below.
The device comprises a p-type silicon substrate ll5 as de- scribed above. Within a part of the substrate a buried n-type layer 220 with a typical thickness in the order of l um and a typical doping concentration in the range of l-10” to l-10” 3 cm' is formed. On top of a part of layer 220, an n-type layer 230b is formed that reaches the surface. Said layer 230b has a thickness around 0.4 um and a doping concentration around l-lols em The leyer 23oh wlll fem the eelleeter ef the bipolar npn transistor.
Within layer 230b a p-type layer 227b is formed that reachesthe surface and forms the base of the bipolar npn transistor.
The p-type base layer 227b has a doping concentration in the 3 range of 5-10” to 5-l0w cm- and the base-collector junction is approximately 0.4 um below surface. Said p-type base layer 227b is enclosed by the collector layer 230b.
Within layer 227b an n+-layer 245 which reaches the surface is formed. The junction depth of said n+ layer is approxi- mately 0.2um and the layer has a typical surface doping con- centration of l-1020 cm%.
Said layer, which is enclosed by the base layer 227b, forms the emitter of the bipolar npn transistor.
The p-type IGFET transistor is located in the n-well 230a with its channel layer 226 in vicinity of the semiconductor surface, right under the gate structure 256. The p+-layer 240 is forming the source of the IGFET and the p+-layer 24la the drain of the IGFET. The junction depths of said p+-layers are approximately' 0.2 um. and the layers have typical surface H:DOCWORK130515 Application textdocx, 2013-05-15 130017SE l3 4 concentrations in the range of l-10” to 5-1019 mn An n+- layer 235 with a typical junction depth of 0.2 um and a typi- 4 cal surface doping concentration of l-1020 cm will serve as body contact to the p-type IGFET transistor and as contact to the n-layer 230a. Said n-layer 230a, which reaches the sur- face, has an approximate depth of 0.4 um and an approximate a doping concentration of l-10” cm Said layer makes contact to layer 220 and leaves space for a p-well 225, on top of layer 220, between layers 230a and 230b.
On top of layer 225 is a highly conductive layer 24lc ar- ranged that interconnect layers 24la and 24lb that forms respective drain and base contacts of the devices. The highlyconductive layer 24lc arranged on top of layer 225 extendsinto layers 230a and 230b to 24la and 24lb, interconnect layersforming respective drain and base contact layers of the devices.
The highly doped drain layer 24la forms an ohmic contact to the IGFET and. the highly' doped. layer 24lb forms an ohmic contact to the base layer 227b of the npn-transistor, where layer 245 is the emitter and layer 230b is the collector. The p+-layer 24lc contain openings before reaching layer 230b leaving space for contacting the collector layer with an n+- layer, 242. The surface of said interconnect layer is prefer- ably shunted by a silicide layer (e.g. TiSi2, CoSi2, NiSi) of low resistivity. As indicated in Fig. 3, the n-layer 230a, the contact n+-layer 235, the p+-source 240, the gate elec-trode 256 and drain layer 24la can be mirrored in the verti- cal plane 222 through the emitter.
In Fig. 4 is shown an alternative preferred embodiment of alateral N-channel IGBT transistor which use STI (ShallowTrench Isolation) layers 3l0, for oxide isolation. These H:DOCWORK130515 Application textdocx, 2013-05-15 130017SE 14 layers are about 0.3 um deep and improve isolation betweenn+- and p+-layers this step can easily be combined with state of the art CMOS technology. Just the bipolar side of the device is shown. In Fig. 4 the reference numerals designate same parts as those already shown in Fig. 2.
The substrate 115 consists of a silicon wafer with or without an epi layer* on top. Said. substrate 115 is preferably' of (100)-orientation. Substrate 115 can also, in an embodiment of the invention, be a Silicon-On-Insulator (SOI) substrate.
Within a part of the substrate a buried n-type layer 120 with a typical thickness in the order of 1 um and a typical doping 4 concentration in the range of 1-10” to 1-10” cm is formed.
On top of a part of layer 120, a p-type layer 125b is formed that reaches the surface. Said. layer 125b has a thickness around 0.4 um and a doping concentration around 1-10” cm%.
The layer 125b will form the collector of the bipolar pnp transistor.
Partly within layer 125b an n-type layer 127b is formed thatreach the surface and forms the base of the bipolar pnp tran- sistor. The n-type base layer 127b has a doping concentration 3 in the range of 5-1017 to 5-1018 cm- and the base-collector junction is approximately 0.4 um below surface. Said n-type base layer 127b is not fully enclosed by the collector layer 125b. Within layer 127b a jp+-layer 145 which reaches the surface is formed. The junction depth of said p+ layer is approximately' 0.2 um. and. the layer has a typical surface doping concentration of 5-10” cm%. Said layer, which is enclosed by the base layer 127b, forms the emitter of the bipolar pnp transistor.
H:DOCWORK130515 Application textdocx, 2013-05-15 130017SE The n-type IGFET, not shown, is separated from the Bipolar transistor by an n-type layer 130 that is placed on top of, and. makes contact to, layer 120. Said. layer reaches the surface and vertically surrounds the p-type layer 125b thatforms the collector of the pnp transistor. The thickness ofsaid layer is approximately 0.4 um and the doping concentra- tion is around 1-10w cm%.
This layer will isolate the bipo-lar _pnp transistor from. the 120. substrate together* with layerThe somewhat longer highly doped drain layer 136a willform an ohmic contact to the n-layer 130 and thus to the baselayer the 127b of the pnp-transistor, where layer 145 is emitter and layer 125b is the collector. The surface of said interconnect layer 136a is preferably shunted by a silicide layer (e.g. TiSi2, CoSi2, NiSi) of low resistivity.
In Fig. 5 is shown an alternative preferred embodiment of alateral P-channel IGBT transistor which use STI (shallowTrench Isolation) layers 310, for oxide isolation. These layers are about 0.3 um deep and improve isolation between n+- and p+-layers, see Fig.5 layers 310. This step can easily be combined with state of the art CMOS technology. In Fig. 5the reference numerals designate same parts as those already shown in Fig. 2.
The device comprises a p-type silicon substrate 115 as de-scribed above. Within a part of the substrate a buried n-typelayer 220 with a typical thickness in the order of 1 um and atypical doping concentration in the range of 1-10” to 1-10” 3 cm' is formed. On top of a part of layer 220, an n-type layer 230b is formed that reach the surface. Said layer 230b has athickness around 0.4 lnn and. a doping' concentration aroundl-lols em The layer 23oh wlll fem the eelleeter ef the bipolar npn transistor.
H:DOCWORK130515 Application textdocx, 2013-05-15 130017SE l6 Within layer 230b a p-type layer 227b is formed that reachesthe surface and forms the base of the bipolar npn transistor.
The p-type base layer 227b has a doping concentration in the 3 range of 5-10” to 5-l0w cm- and the base-collector junction is approximately 0.4 um below the surface. Said p-type base layer 227b is not fully enclosed by the collector layer 230b.
Within layer 227b an n+-layer 245 which reaches the surface is formed. The junction depth of said n+-layer is approxi- mately' 0.2 um. and. the layer* has a typical surface doping 4 concentration of l-10% cm Said layer, which is enclosed by the base layer 227b, forms the emitter of the bipolar npn transistor.
The p-type IGFET transistor is located in the n-well 230a with its channel layer 236 in vicinity of the semiconductor surface, right under the gate structure 256. The p+-layer 240 is forming the source of the IGFET and the p+-layer 24la the drain of the IGFET. The junction depths of said p+ layers are approximately' 0.2 um. and the layers have typical surface concentrations in the range of l-10” to 5-lfg cmf. An n+- layer 235 with a typical junction depth of 0.2 um and a typi- 4 cal surface doping concentration of l-1020 cm will serve as body contact to the p-type IGFET transistor and as contact to the n-layer 230a. Said n-layer 230a, which reaches the sur- face, has an approximate depth of 0.4 um and an approximate a doping concentration of l-10” cm Said layer makes contact to layer 220 and leaves space for a p-well 225, on top oflayer 220, between layers 230a and 230b.The somewhat longer highly doped drain layer 24la, that ex- tends into layer 225 will form an ohmic contact 24lb to thebase layer 227b of the npn-transistor, where layer 245 is the emitter and layer 230b is the collector. The surface of said H:DOCWORK130515 Application textdocx, 2013-05-15 130017SE l7 interconnect layer is preferably shunted by a silicide layer TiSi2, CoSi2, NiSi) of low resistivity. (e.g.
The described devices and functions that have been detailedabove as part of the invention are very different from the prior art device of FIG. lA, in that the drift layer 20 has in our embodiments been replaced by a somewhat extended drain diffusion having a very low resistivity, typically 20 ohm/square, as compared to the high resistivity, typically l0 kohm, of the prior art drift layer. Conductivity modulation, being an essential function of prior-art devices, will there- fore not occur. Furthermore, in contrast to the prior art devices, the transistor structures implemented in the inven- tion are all of standard. type and. do not require special processing and layout steps and modifications. The use of avertical bipolar transistor' in combination with a lateralIGFET and. the elimination. of any lateral _pnp- and/or* npn-transistor(s), the latter being an essential part of priorart devices, reduce the risk of latch-up problems and distin- guishes our invention from prior art.
ReferenceslN.Sakurai, M.Mori, T.Tanaka, “US Pat 5l26806” 2B. Bakeroot, J. Doutreloigne, P. Vanmeerbeek, P. Moens, “A New Lateral-IGBT Structure with a Wider Safe Operating Ar- ea", IEEE Electron Device Letters 28, 4l6-418 (2007).3E.K.c. Tee, Aﬁöike, s.J. Piikingtøn, D.K. Pai, Ni. Yew,W.A.W.Z. Abidin, “A Review of techniques used in Lateral Insulated Gate Bipolar Transistors (LIGBT)”.
H:DOCWORK130515 Application textdocx, 2013-05-15 130017SE

权利要求:
Claims (14)
[1] 1. A lateral IGBT transistor comprising a bipolar transistorand an IGFET, where the IGFET can be of conventional type orbe of the extended drain type, characterized by:-a low resistive connection between the drain of the IGFETand the base of the bipolar transistor, and;-an isolating layer arranged between the IGFET and the bipo-lar transistor,thereby providing latch immunity.
[2] 2. The lateral IGBT transistor according to claim 1, wherein the lateral IGBT transistor is a lateral n-channel IGBT tran- sistor (100) comprising a bipolar PNP transistor (102) and an-channel IGFET (101), wherein the lateral n-channel IGBTtransistor (100) comprises: -a semiconductor substrate (115); and -an insulating layer (120) buried in the semiconductor sub-strate and at least covering the bipolar PNP transistor and(136a) (102) at least portion of a drain layer of the IGFET;and wherein the bipolar PNP transistor (125b) comprises:-a p-type collector layer(120) arranged on top of a portion of insulating layer and extending to the upper surface of the semiconductor substrate (115), forming the collector of the bipolar PNP transistor;-an n-type base layer (127b) (125b) arranged within the p-type col- lector layer and extending to the upper surface of the semiconductor substrate (115), forming the base of the bipo-lar PNP transistor; and-a. p-type emitter layer (145) arranged. within n-type base layer (127b) and extending to the upper surface of the semi- conductor substrate (115), forming the emitter of the bipolarPNP transistor; and wherein the n-channel IGFET comprises: H:DOCWORK130515 Application textdocx, 2013-05-15 130017SE 19 -a p-well (125a), extending from the upper surface of thesemiconductor substrate (115) into the semiconductor sub-strate (115); -a channel layer (126) in vicinity of the upper surface of the semiconductor substrate (115) and arranged under a gatestructure (156), -an n-type source layer (135) forming the source of the n-channel IGFET (101); and -an n-type drain layer (136a) forming the drain of the n- channel IGFET (101); the lateral n-channel IGBT transistor (100) characterized by:-an n-well layer (130) adjacent to the p-well (125a) of then-channel IGFET (101) and to the collector layer (125b) of (102), and wherein the n-type base(l25b), (125b) the bipolar PNP transistor layer (127b) is enclosed by the collector layer and the n-well layer (130) surrounds the collector layer(120), (102); and is in contact with the insulating layer providing device isolation of the bipolar PNP transistor and(136c) (136b) -a low resistive interconnect layer extending from the drain layer (136a) to the base layer forming low re- interconnect and. simultaneously' providing' an ohmic (136b), sistive contact to the base layer the low resistive intercon- nect layer (136c) arranged at least partly over the p-well(125a) and at least partly over the collector layer (125b)and at least partly over the n-well layer (130).
[3] 3. The lateral N-channel IGBT transistor (100) according to clain1 2, characterized. in that the semiconductor* substrate(115) comprises buried oxide layer and the insulating layer(120) is formed. by the oxide layer* that extends over the complete substrate.
[4] 4. The lateral N-channel IGBT transistor (100) according to claim 2, characterized in that the interconnect layer (136c) H:DOCWORK130515 Application textdocx, 2013-05-15 130017SE is provided with openings to allow contact to the collectorlayer (125b).
[5] 5. The lateral N-channel IGBT transistor (100) at least the according to claim. 2, characterized in that interconnect layer (136c) is shunted by a silicide layer of low resistivi- ty.
[6] 6. The lateral N-channel IGBT transistor (100) according toclaim 2, characterized in that the interconnect layer (136c)is shunted by a metal bridge spanning from drain layer (136a) to base layer (136b).
[7] 7. The lateral N-channel IGBT transistor (100) according toclaim 2, (150) further' provided. with. a p-type collector contact(125b)(145) in contact with p-type layer and oxide (310) layersurrounding the emitter and the (150), isolation layersand in that the interconnect (136b) is collector contact layer(136c)(130). layer and. base layer replaced. by n-well layer
[8] 8. The lateral N-channel IGBT transistor (100) according tocharacterized in that the IGBT structure is mirrored (122) claim 2,vis-a-vis an imaginary vertical plane through the emit-ter.
[9] 9. The lateral IGBT transistor according to claim 1, wherein the lateral IGBT transistor is a lateral p-channel IGBT tran- sistor (200) comprising a bipolar NPN transistor (202) and ap-channel IGFET (201), wherein the lateral p-channel IGBTtransistor (200) comprises: -a semiconductor substrate (220) (115): -a buried n-layer arranged in the semiconductor sub- strate (115) at least covering' the bipolar* NPN' transistor H:DOCWORK130515 Application textdocx, 2013-05-15 130017SE 2l (202) and at least portion of a drain layer (24la) of theIGFET; andwherein the bipolar NPN transistor (202) comprises: (230b)(220) -an n-type collector layer arranged on top of a por-and a portion extending to(115), (202); tion of the buried n-layerthe upper surface of the semiconductor substrate form-ing the collector of the bipolar NPN transistor -a p-type base layer (227b) (230b) arranged within the n-type col- lector layer and extending to the upper surface of the semiconductor substrate (ll5), forming the base of the bipo- lar NPN transistor (202); and -an n-type emitter layer (245) arranged. within. base layer(227b) and extending' to the upper semiconductor substrate(ll5), forming the emitter of the bipolar NPN transistor; and wherein the p-channel IGFET (20l) (230a) comprises: -an n-well extending' fronl the upper* surface of the semiconductor substrate (ll5) into the semiconductor sub- strate;(226) -a channel layer in vicinity of the upper surface of the semiconductor substrate (ll5) and arranged under a gatestructure (256); -a p-type source layer (240) is forming the source of the p-channel IGFET (20l); and -a. p-type drain layer (24la) forming' the drain of the p- channel IGFET (20l); (200) characterized by:(230a) (230b) the lateral p-channel IGBT transistor-a p-well layer (225)(201) adjacent to the p-well of the p- channel IGFET and to the collector layer of the bipolar NPN transistor (202), (227b) and. wherein the p-type base(230b)(230b) layer is enclosed by the collector layer and the p-well layer (225) surrounds the collector layer(220) and the NPN bipolar and. is in contact with. the buried. n-layer providing isolation between IGFET (201) (202); device transistor and H:DOCWORK130515 Application textdocx, 2013-05-15 130017SE 22 (241c)(241b) -a low resistive interconnect layer extending from the drain layer (241a) to the base layer forming low re- interconnect and. simultaneously' providing' an ohmic (227b), sistivecontact to the base layer the low resistive intercon-nect layer (241c) (230a), arranged at least partly over the n-well at least partly over the collector layer (230b) and at least partly over the p-well layer (225).
[10] 10. The lateral P-channel IGBT transistor (200) according to clain1 9, characterized. in that the semiconductor* substrate (115) comprises a buried oxide layer forming an insulating layer (220) that extends over the complete substrate.
[11] 11. The lateral P-channel IGBT transistor (200) according to claim 9, characterized in that the interconnect layer (241c) is provided with openings to allow contact to the collectorlayer (230b).
[12] 12. The lateral P-channel IGBT transistor (200) at least the according to claim. 9, characterized in that interconnect layer (241c) is shunted by a silicide layer of low resistivi- ty.
[13] 13. The lateral P-channel IGBT transistor (100) according toclaim 9, characterized in that the interconnect layer (241c)is shunted by a metal bridge spanning from drain layer (241a) to base layer (241b).
[14] 14. The lateral P-channel IGBT transistor (100) according toclaim 9, (250) further' provided. with. a n-type collector contact(230b)(145) in contact with n-type layer and oxide (310) layersurrounding the emitter and the (250), isolation layers collector contact layer and in that the interconnect H:DOCWORK130515 Application textdocx, 2013-05-15 130017SE 23 layer (2410) and. base layer (24lb) is replaced. by p-welllayer (225). H:DOCWORK130515 Application textdocx, 2013-05-15 130017SE

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法律状态:

优先权:

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SE1350595A|SE537230C2|2013-05-16|2013-05-16|Bipolar transistor amplifier circuit with isolated gate|SE1350595A| SE537230C2|2013-05-16|2013-05-16|Bipolar transistor amplifier circuit with isolated gate|

CN201480027380.6A| CN105264666B|2013-05-16|2014-05-12|Insulated gate bipolar transistor amplifier circuit|

EP14798633.5A| EP2997601A4|2013-05-16|2014-05-12|An insulated gate bipolar transistor amplifier circuit|

US14/889,876| US9608097B2|2013-05-16|2014-05-12|Insulated gate bipolar transistor amplifier circuit|

JP2016513901A| JP6389247B2|2013-05-16|2014-05-12|Insulated gate bipolar transistor amplifier circuit|

PCT/SE2014/050577| WO2014185852A1|2013-05-16|2014-05-12|An insulated gate bipolar transistor amplifier circuit|

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